On July 14, EastCore unveiled its first AI chip DF1000 in Shanghai, built on a software-defined architecture with 3D stacked near-memory computing – designed to bypass reliance on advanced process nodes and HBM.
Led by veteran semiconductor professor Wei Shaojun, the company positions DF1000 as a response to constrained supply chains, where domestic access to sub-14nm process, high-end HBM, and advanced equipment remains restricted.
The DF1000 rests on three core innovations:
Software-defined Tile architecture with full-stack reconfigurability, improving hardware utilization via dataflow-driven parallel processing and time-division multiplexing – reducing dependence on leading-edge lithography.
Logic-memory 3D hybrid bonding that shortens interconnect pitch, delivering bandwidth multiple times higher than conventional designs and scaling capacity through stacking layers.
Infinity Chiplet 3.5D+ expansion optimizing multi-die stacking to save I/O and package space, breaking large-scale cluster communication bottlenecks.
Fabricated on 14nm, DF1000 achieves 520 TFLOPS BF16 compute, 6.4 TB/s memory bandwidth, and 900 GB/s scale-up inter-chip bandwidth. While absolute compute trails NVIDIA’s Hopper, memory bandwidth is a clear advantage – particularly for LLM inference decode stages, reducing latency and boosting throughput in long-context, high-concurrency scenarios. The chip has demonstrated stable operation on LLaMA3 and DeepSeek models.
Roadmap: DF2000 (14nm, 2x performance) in Q4 2026, targeting Hopper-class metrics; DF3000 in Q4 2027, aiming at B-series levels.
EastCore also launched a full commercial portfolio – accelerators, modules, supernodes, AI servers, and clusters – supported by its self-developed CAAP software stack compatible with major open-source models and frameworks, enabling thousand-card to ten-thousand-card deployments.
The company, valued at RMB 12.28 billion after its Series A+ in April 2026, plans a Series B in Q4.
Challenges remain: software-defined reconfigurable computing faces interconnect overhead, dynamic reconfiguration latency, and ease-of-use tradeoffs. 3D hybrid bonding yields and stacking costs scale with layer count. The long-term ceiling is still constrained by domestic manufacturing capability. And the biggest hurdle is software ecosystem – building compiler, operator library, and developer community around a non-GPU architecture takes years.
Still, DF1000 proves a complete flow from research to tape-out to system integration – offering a differentiated path for domestic AI compute under supply constraints.
From ICgoodFind: Not every AI chip needs 3nm and HBM. EastCore just showed that architecture can beat process – at least on bandwidth. The real bet is whether software catches up to silicon.
